Compatible Systems Octal V.35 - 10/100 RIOP Instruction Manual download pdf (Page 121)

ATLAS 800 Series System Manual Quad Nx56/64 Option Module

PLL/FIFO

Read security: 5

Displays the Phase Lock Loop (PLL) and FIFO status.

Port Indicates the operating port.

PLL/FIFO Displays the state of the PLL and FIFO systems.

Configuration

Write security: 3; Read security: 5

All of the following configurable parameters apply to the individual V.35 ports.

Port Read security: 5

Displays the port number.

Name Accepts any alpha-numeric name up to 17 characters long, to uniquely identify

each port on the Quad V.35 Option Module.

Clk +/- Controls the clock used by the ATLAS 800 Series to accept the transmit (TX)

data from the DTE. This is usually set to

NORMAL. If the interface cable is long,

causing a phase shift in the data, the clock can be set to

INVERTED. This switches

the phase of the clock, which compensates for a long cable.

Data Controls the inverting of the DTE data. This inversion can be useful when

operating with a high-level data link control (HDLC) protocol (often used as a

means to ensure 1s density). Select either

NORMAL or INVERTED. Data inversion

configuration must match at both ends of the circuit.

CTS Determines the behavior of the Clear To Send (CTS) signal. If set to Normal,

CTS will follow the value of Request To Send (RTS). If set to Forced On, CTS

will always be asserted.

DCD Determines the behavior of the Data Carrier Detect (DCD) signal, also called

RLSD on V.35 interfaces. If set to Normal, DCD will generally be asserted

when the interface is capable of passing data. If set to Forced On, DCD will

State Description

Lock

PLL is locked (This is required to transfer data.)

RXE

Receive data FIFO empty.

RXF

Receive data FIFO full.

TXE

Transmit data FIFO empty.

TXF

Transmit data FIFO full.

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Compatible Systems Octal V.35 - 10/100 RIOP Instruction Manual Page 121